Work on FPGA designs by combining open-source FPGA methodology with proprietary technologies that enable a faster design-to-silicon turnaround.
Use the latest innovative AI-enhanced EDA tools to provide the most optimized designs.
What’s in it for you:
- Market Competitive Salary package and incentives based on performance
- You will be part of a highly qualified and professional team.
- Working with international customers from the U.S., China, and/or South Korea.
- Clearly defined career growth path and technical roadmap for personal growth.
- Greenfield projects with well-defined product roadmaps
What you'll do:
- Develop pre-Silicon functional validation tests to verify system will meet design requirements.
- Create test plans for RTL validation, defining and running system simulation models, and finding and implementing corrective measures for failing RTL tests.
- Do the SoC-level and/or block-level and/or IP verification.
- Build and continuously reform verification infrastructure and methodologies to meet the demands of next generation SoCs
- Define, develop, and execute Verification plans for Complex IPs at SoC level.
- Analyze and use results to modify testing and improve the code and functional coverage. Implement and execute coverage driven verification on SoC’s.
- Work with architects, RTL designers, FPGA, emulation engineers to ensure that verification requirements are met for each project
What you'll need:
- 8-10+ years of SoC design verification experience.
- B.S or M.S with Electrical/Computer Engineering or related field.
- Proficient in UVM/OVM verification methodologies.
- Deep understanding of SoC verification concepts.
- Experience with verification of SoCs with embedded processors or CPU verification.
- Experience with PCIe, SerDes, Bus Fabric, NOC is a plus.
- Experience with complete verification cycle from design conception to tape-out of complex SoCs.
- Should be a teammate with excellent written and verbal communication skills.
For a detailed conversation, Apply NOW and let's have a chat.