Work on FPGA designs by combining open-source FPGA methodology with proprietary technologies that enable a faster design-to-silicon turnaround.
Use the latest innovative AI-enhanced EDA tools to provide the most optimized designs.
What’s in it for you:
- Market Competitive Salary package and incentives based on performance
- You will be part of a highly qualified and professional team.
- Working with international customers from the U.S., China, and/or South Korea.
- Clearly defined career growth path and technical roadmap for personal growth.
- Greenfield projects with well-defined product roadmaps
What you'll do:
- Develop SoC/IP microarchitecture requirements documents meeting architecture requirements and work with stakeholders (architecture, verification, validation) to sign off on microarchitecture.
- RTL design and debug of complex blocks in Verilog / System Verilog.
- Work in systems such as: Synthesis, Timing Analysis, Low Power design techniques, Asynchronous design, and DFT.
- Work with physical design team for timing and PnR closure.
- Do technical review of Functional specification, micro-arch and RTL Code.
- Work closely with local and remote verification teams to develop verification plans, write assertions, debug failures, and complete 100% code and functional coverage.
What you'll need:
- 8-10+ years of SoC/ASIC design experience.
- B.S or M.S. in Electrical/Computer Engineering or related technical field
- Experience with PCIe, SerDes, Bus Fabric, NOC design is a plus.
- Experience with designing SoCs with ARM based embedded processors.
- Experience in micro architecture definition, RTL coding and PPA analysis
- Proficiency in RTL design, DFT, synthesis, timing closure, SoC integration and verification.
- Low Power Methodology and automotive safety knowledge is a plus.
- Experience in Interface Standards (PCIE, SerDes, USB, Ethernet).
- Experience in AMBA bus fabric standards (APB, AHB, AXI, CCI).
For a detailed conversation, Apply NOW and let's have a chat.