Work on FPGA designs by combining open-source FPGA methodology with proprietary technologies that enable a faster design-to-silicon turnaround.
Use the latest innovative AI-enhanced EDA tools to provide the most optimized designs.
What’s in it for you:
- Market Competitive Salary package and incentives based on performance
- You will be part of a highly qualified and professional team.
- Working with international customers from the U.S., China, and/or South Korea.
- Clearly defined career growth path and technical roadmap for personal growth.
- Greenfield projects with well-defined product roadmaps
What you'll do:
- Synthesize, Floorplan, APR and signoff partitions assigned to you.
- Perform various quality checks to ensure signoff (timing, physical verification, IR drop, Functional Equivalence check) requirements are met
- Analyze reports and utilize scripts to debug, automate tasks and provide feedback to relevant stakeholders
- Work closely with the Architecture and Design team to understand, address and converge partition
- Drive Implementation requirements Influence & Continuous seek to improve the RTL to GDSII methodology
What you'll need:
- BSEE or equivalent with 7+ years/MSEE or equivalent with 5+ years of design experience in the structural/physical design domain
- Have multiple tape-out experiences in deep submicron, preferably experience in 14nm and below
- Proficient in aspects of physical design from RTL hand-off through streaming out a clean GDSII (such as Floorplan, Synthesis, Auto Place & Route, Signal Integrity Verification, Clock Tree Synthesis, Performance Verification, Reliability Verification, Power Analysis & Optimisation, Timing Closure etc).
- Experience in relevant VLSI structural/physical design methodology flows and relevant EDA tools will be an advantage
- Experience in Block-level Implementation and Full-chip floor-planning and power grid planning. Previous experience in a key technical leading role in the development and delivery of leading-edge physical databases for ASICs, SoCs or IPs will be an advantage
- Experienced in industry RTL to GDSII tools: Design Compiler, IC Compiler II, Fusion Compiler, PrimeTime, etc
- Hands-on expertise with scripting languages such as Perl, TCL, and knowledge of hardware description languages of VHDL & Verilog.
- Possess strong initiative, analytical/problem-solving skills, team working skills, ability to multitask and be able to work within a diverse team environment.
For a detailed conversation, Apply NOW and let's have a chat.