Senior Manager, IP Functional Modeling

Work on FPGA designs by combining open-source FPGA methodology with proprietary technologies that enable a faster design-to-silicon turnaround.

Use the latest innovative AI-enhanced EDA tools to provide the most optimized designs.

What’s in it for you:

  • Market Competitive Salary package and incentives based on performance
  • You will be part of a highly qualified and professional team.
  • Working with international customers from the U.S., China, and/or South Korea.
  • Clearly defined career growth path and technical roadmap for personal growth.
  • Greenfield projects with well-defined product roadmaps

What you'll do:

  • Build, manage and mentor IP Modeling team responsible for IP Functional Modeling and development used in FPGA design. Drive microarchitecture and architecture development and design execution.
  • Review IP micro-architecture and development to meet architecture spec for Cycle accuracy and Instruction accuracy.
  • Design and develop Behavioral and Structured IP Models for functional and performance tuning to be used in Design Verification Test Benches using SystemC, System Verilog and UVM methodologies.
  • Drive key metrics and milestones to meet IP development tape out schedule.
  • Communicate efficiently between design teams, logic, process, product / test engineering and architecture teams.
  • Ability to provide mentorship and guidance to team members.
  • Work closely with DV team in reviewing test plans, and fixing design issues optimally.
  • Ensure resourcing is aligned to meet execution deliverables.

What you'll need:

  • M.S. in Electrical/Computer Engineering or related technical field
  • 5+ years of experience in managing Bus Functional and IP Modeling design and development teams and working across multiple projects.
  • Experienced with interpreting functional specs and developing architecture, and microarchitecture for IP Modeling.
  • A clear understanding of IP Model development flows, and verification methodologies
  • Proficiency in Verilog RTL development, integration, and verification.
  • A strong leader with experience in working with a distributed team.

For a detailed conversation, Apply NOW and let's have a chat.